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High Bandwidth Memory (HBM) is a pc memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. RAM in upcoming CPUs, and FPGAs and in some supercomputers (such because the NEC SX-Aurora TSUBASA and Fujitsu A64FX). HBM achieves increased bandwidth than DDR4 or GDDR5 while using less energy, and in a substantially smaller form factor. This is achieved by stacking up to eight DRAM dies and an elective base die which might embody buffer circuitry and test logic. The stack is commonly linked to the memory controller on a GPU or CPU through a substrate, resembling a silicon interposer. Alternatively, the memory die could possibly be stacked directly on the CPU or GPU chip. Throughout the stack the dies are vertically interconnected by by means of-silicon vias (TSVs) and microbumps. The HBM technology is similar in precept however incompatible with the Hybrid Memory Cube (HMC) interface developed by Micron Technology. HBM memory bus may be very broad in comparison to other DRAM memories similar to DDR4 or GDDR5.

An HBM stack of four DRAM dies (4-Hi) has two 128-bit channels per die for a complete of eight channels and a width of 1024 bits in complete. A graphics card/GPU with 4 4-Hi HBM stacks would due to this fact have a memory bus with a width of 4096 bits. Compared, the bus width of GDDR reminiscences is 32 bits, with 16 channels for a graphics card with a 512-bit Memory Wave App interface. HBM helps up to four GB per package deal. The bigger variety of connections to the memory, relative to DDR4 or GDDR5, required a brand new methodology of connecting the HBM memory to the GPU (or different processor). AMD and Nvidia have each used objective-built silicon chips, known as interposers, to connect the memory and GPU. This interposer has the added benefit of requiring the memory and processor to be bodily shut, lowering memory paths. However, as semiconductor gadget fabrication is considerably costlier than printed circuit board manufacture, this adds cost to the ultimate product.

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into impartial channels. The channels are utterly impartial of one another and are not essentially synchronous to one another. The HBM DRAM uses a wide-interface architecture to achieve excessive-speed, low-power operation. Each channel interface maintains a 128-bit data bus operating at double data rate (DDR). HBM helps transfer rates of 1 GT/s per pin (transferring 1 bit), yielding an total package bandwidth of 128 GB/s. The second generation of High Bandwidth Memory Wave, HBM2, additionally specifies up to eight dies per stack and doubles pin switch charges as much as 2 GT/s. Retaining 1024-bit vast entry, HBM2 is ready to achieve 256 GB/s memory bandwidth per package. The HBM2 spec allows up to 8 GB per bundle. HBM2 is predicted to be especially helpful for performance-sensitive consumer applications equivalent to virtual actuality. On January 19, 2016, Samsung introduced early mass manufacturing of HBM2, at up to eight GB per stack.

In late 2018, JEDEC introduced an update to the HBM2 specification, offering for increased bandwidth and capacities. Up to 307 GB/s per stack (2.5 Tbit/s effective knowledge charge) is now supported in the official specification, although merchandise working at this pace had already been obtainable. Additionally, the replace added support for 12-Hi stacks (12 dies) making capacities of up to 24 GB per stack potential. On March 20, 2019, Samsung introduced their Flashbolt HBM2E, featuring eight dies per stack, a transfer rate of 3.2 GT/s, providing a complete of 16 GB and 410 GB/s per stack. August 12, 2019, SK Hynix introduced their HBM2E, Memory Wave App that includes eight dies per stack, a switch fee of 3.6 GT/s, offering a total of sixteen GB and 460 GB/s per stack. On July 2, 2020, SK Hynix announced that mass manufacturing has begun. In October 2019, Samsung introduced their 12-layered HBM2E. In late 2020, Micron unveiled that the HBM2E commonplace would be updated and alongside that they unveiled the following customary referred to as HBMnext (later renamed to HBM3).